ACALL addr11Absolute subroutine call  (details)
Call subroutine at addr
affected flags: C, OV, AC
MnemonicOperandsBytesPeriodsDescription
ACALLaddr11224Absolute Subroutine Call  (hex codes)
Instruction1. Byte2. Byte
ACALL code addr11code addr
ACALL code addr31code addr
ACALL code addr51code addr
ACALL code addr71code addr
ACALL code addr91code addr
ACALL code addrB1code addr
ACALL code addrD1code addr
ACALL code addrF1code addr

ACALL unconditionally calls a subroutine located at the indicated address. The instruction increments the PC twice to obtain the address of the following instruction, then pushes the 16-bit result onto the stack (low-order byte first) and increments the Stack Pointer twice. The destination address is obtained by successively concatenating the five high-order bits of the incremented PC, opcode bits 7 through 5, and the second byte of the instruction. The subroutine called must therefore start within the same 2 K block of the program memory as the first byte of the instruction following ACALL. No flags are affected.

ADD A,<src-byte>Add Byte to Accumullator  (details)
A = A + <byte>
affected flags: C, OV, AC
addresing modes: direct, indirect, register, constant
MnemonicOperandsBytesPeriodsDescription
ADDA,Rn112Add register to Accumulator  (hex codes)
Instruction1. Byte
ADD A,R028
ADD A,R129
ADD A,R22A
ADD A,R32B
ADD A,R42C
ADD A,R52D
ADD A,R62E
ADD A,R72F
ADDA,direct212Add direct byte to Accumulator  (hex codes)
Instruction1. Byte2. Byte
ADD A,data addr25data addr
ADDA,@Ri112Add indirect RAM to Accumulator  (hex codes)
Instruction1. Byte
ADD A,@R026
ADD A,@R127
ADDA,#data212Add immediate data to Accumulator  (hex codes)
Instruction1. Byte2. Byte
ADD A,#data24#data

ADD adds the byte variable indicated to the Accumulator, leaving the result in the Accumulator. The carry and auxiliary-carry flags are set, respectively, if there is a carry-out from bit 7 or bit 3, and cleared otherwise. When adding unsigned integers, the carry flag indicates an overflow occurred. OV is set if there is a carry-out of bit 6 but not out of bit 7, or a carry-out of bit 7 but not bit 6; otherwise, OV is cleared. When adding signed integers, OV indicates a negative number produced as the sum of two positive operands, or a positive sum from two negative operands.

ADDC A,<src-byte>Add Byte to Accumullator with Carry flag  (details)
A = A + <byte> + C
affected flags: C, OV, AC
addresing modes: direct, indirect, register, constant
MnemonicOperandsBytesPeriodsDescription
ADDCA,Rn112Add register to Accumulator with Carry  (hex codes)
Instruction1. Byte
ADDC A,R038
ADDC A,R139
ADDC A,R23A
ADDC A,R33B
ADDC A,R43C
ADDC A,R53D
ADDC A,R63E
ADDC A,R73F
ADDCA,direct212Add direct byte to Accumulator with Carry  (hex codes)
Instruction1. Byte2. Byte
ADDC A,data addr35data addr
ADDCA,@Ri112Add indirect RAM to Accumulator with Carry  (hex codes)
Instruction1. Byte
ADDC A,@R036
ADDC A,@R137
ADDCA,#data212Add immediate data to Acc with Carry  (hex codes)
Instruction1. Byte2. Byte
ADDC A,#data34#data

ADDC simultaneously adds the byte variable indicated, the carry flag and the Accumulator contents, leaving the result in the Accumulator. The carry and auxiliary-carry flags are set respectively, if there is a carry-out from bit 7 or bit 3, and cleared otherwise. When adding unsigned integers, the carry flag indicates an overflow occurred. OV is set if there is a carry-out of bit 6 but not out of bit 7, or a carry-out of bit 7 but not out of bit 6; otherwise OV is cleared. When adding signed integers, OV indicates a negative number produced as the sum of two positive operands or a positive sum from two negative operands. Four source operand addressing modes are allowed: register, direct, register-indirect, or immediate.

AJMP addr11Absolute Jump  (details)
affected flags: C, OV, AC
MnemonicOperandsBytesPeriodsDescription
AJMPaddr11224Absolute Jump  (hex codes)
Instruction1. Byte2. Byte
AJMP code addr01code addr
AJMP code addr21code addr
AJMP code addr41code addr
AJMP code addr61code addr
AJMP code addr81code addr
AJMP code addrA1code addr
AJMP code addrC1code addr
AJMP code addrE1code addr

AJMP transfers program execution to the indicated address, which is formed at run-time by concatenating the high-order five bits of the PC (after incrementing the PC twice), opcode bits 7 through 5, and the second byte of the instruction. The destination must therfore be within the same 2 K block of program memory as the first byte of the instruction following AJMP.

ANL <dest-byte>,<src-byte>Logical AND for Byte variables  (details)
affected flags: C, OV, AC
MnemonicOperandsBytesPeriodsDescription
ANLA,Rn112AND Register to Accumulator  (hex codes)
Instruction1. Byte
ANL A,R058
ANL A,R159
ANL A,R25A
ANL A,R35B
ANL A,R45C
ANL A,R55D
ANL A,R65E
ANL A,R75F
ANLA,direct212AND direct byte to Accumulator  (hex codes)
Instruction1. Byte2. Byte
ANL A,data addr55data addr
ANLA,@Ri112AND indirect RAM to Accumulator  (hex codes)
Instruction1. Byte
ANL A,@R056
ANL A,@R157
ANLA,#data212AND immediate data to Accumulator  (hex codes)
Instruction1. Byte2. Byte
ANL A,#data54#data
ANLdirect,A212AND Accumulator to direct byte  (hex codes)
Instruction1. Byte2. Byte
ANL data addr,A52data addr
ANLdirect,#data324AND immediate data to direct byte  (hex codes)
Instruction1. Byte2. Byte3. Byte
ANL data addr,#data53data addr#data

ANL performs the bitwise logical-AND operation between the variables indicated and stores the results in the destination variable. No flags are affected. The two operands allow six addressing mode combinations. When the destination is the Accumulator, the source can use register, direct, register-indirect, or immediate addressing; when the destination is a direct address, the source can be the Accumulator or immediate data. Note: When this instruction is used to modify an output port, the value used as the original port data will be read from the output data latch, not the input pins.

ANL C,<src-bit>Logical OR for Carry flag and Bit data  (details)
C = C AND bit
affected flags: C, OV, AC
MnemonicOperandsBytesPeriodsDescription
ANLC,bit224AND direct bit to CARRY  (hex codes)
Instruction1. Byte2. Byte
ANL C,bit addr82bit addr
ANLC,/bit224AND complement of direct bit to Carry  (hex codes)
Instruction1. Byte2. Byte
ANL C,/bit addrB0/bit addr

If the Boolean value of the source bit is a logical 0, then ANL C clears the carry flag; otherwise, this instruction leaves the carry flag in its current state. A slash ( / ) preceding the operand in the assembly language indicates that the logical complement of the addressed bit is used as the source value, but the source bit itself is not affected. No other flags are affected. Only direct addressing is allowed for the source operand.

CJNE <dest-byte>,<src-byte>, relCompare and jump if not equal  (details)
Jump if <byte> <> #data
affected flags: C
addresing modes: indirect, register
MnemonicOperandsBytesPeriodsDescription
CJNEA,direct,rel324Compare direct byte to Acc and Jump if Not Equal  (hex codes)
Instruction1. Byte2. Byte3. Byte
CJNE A,data addr,code addrB5data addrcode addr
CJNEA,#data,rel324Compare immediate to Acc and Jump if Not Equal  (hex codes)
Instruction1. Byte2. Byte3. Byte
CJNE A,#data,code addrB4#datacode addr
CJNERn,#data,rel324Compare immediate to register and Jump if Not Equal  (hex codes)
Instruction1. Byte2. Byte3. Byte
CJNE R0,#data,code addrB8#datacode addr
CJNE R1,#data,code addrB9#datacode addr
CJNE R2,#data,code addrBA#datacode addr
CJNE R3,#data,code addrBB#datacode addr
CJNE R4,#data,code addrBC#datacode addr
CJNE R5,#data,code addrBD#datacode addr
CJNE R6,#data,code addrBE#datacode addr
CJNE R7,#data,code addrBF#datacode addr
CJNE@Ri,#data,rel324Compare immediate to indirect and Jump if Not Equal  (hex codes)
Instruction1. Byte2. Byte3. Byte
CJNE @R0,#data,code addrB6#datacode addr
CJNE @R1,#data,code addrB7#datacode addr

CJNE compares the magnitudes of the first two operands and branches if their values are not equal. The branch destination is computed by adding the signed relative-displacement in the last instruction byte to the PC, after incrementing the PC to the start of the next instruction. The carry flag is set if the unsigned integer value of &lt;dest-byte&gt; is less than the unsigned integer value of &lt;src-byte&gt;; otherwise, the carry is cleared. Neither operand is affected. The first two operands allow four addressing mode combinations: the Accumulator may be compared with any directly addressed byte or immediate data, and any indirect RAM location or working register can be compared with an immediate constant.

CLR AClear Accumulator  (details)
affected flags: C, OV, AC
MnemonicOperandsBytesPeriodsDescription
CLRA112Clear Accumulator  (hex codes)
Instruction1. Byte
CLR AE4

CLR A clears the Accumulator (all bits set to 0). No flags are affected

CLR bitClear Bit data  (details)
bit = 0
affected flags: C, OV, AC
MnemonicOperandsBytesPeriodsDescription
CLRC112Clear Carry  (hex codes)
Instruction1. Byte
CLR CC3
CLRbit212Clear direct bit  (hex codes)
Instruction1. Byte2. Byte
CLR bit addrC2bit addr

CLR bit clears the indicated bit (reset to 0). No other flags are affected. CLR can operate on the carry flag or any directly addressable bit.

CPL AComplement Accumulator  (details)
affected flags: C, OV, AC
MnemonicOperandsBytesPeriodsDescription
CPLA112Complement Accumulator  (hex codes)
Instruction1. Byte
CPL AF4

CPLA logically complements each bit of the Accumulator (one’s complement). Bits which previously contained a 1 are changed to a 0 and vice-versa. No flags are affected.

CPL bitComplement Bit data  (details)
bit = NOT bit
affected flags: C, OV, AC
MnemonicOperandsBytesPeriodsDescription
CPLC112Complement Carry  (hex codes)
Instruction1. Byte
CPL CB3
CPLbit212Complement direct bit  (hex codes)
Instruction1. Byte2. Byte
CPL bit addrB2bit addr

CPL bit complements the bit variable specified. A bit that had been a 1 is changed to 0 and vice-versa. No other flags are affected. CLR can operate on the carry or any directly addressable bit. Note: When this instruction is used to modify an output pin, the value used as the original data is read from the output data latch, not the input pin.

DA ADecimal adjust Accumulator for Addition  (details)
Decimal Adjust
affected flags: C
note: Accumulator only
MnemonicOperandsBytesPeriodsDescription
DAA112Decimal Adjust Accumulator  (hex codes)
Instruction1. Byte
DA AD4

DA A adjusts the eight-bit value in the Accumulator resulting from the earlier addition of two variables (each in packed-BCD format), producing two four-bit digits. Any ADD or ADDC instruction may have been used to perform the addition. If Accumulator bits 3 through 0 are greater than nine (xxxx1010-xxxx1111), or if the AC flag is one, six is added to the Accumulator producing the proper BCD digit in the low-order nibble. This internal addition sets the carry flag if a carry-out of the low-order four-bit field propagates through all high-order bits, but it does not clear the carry flag otherwise. If the carry flag is now set, or if the four high-order bits now exceed nine (1010xxxx-1111xxxx), these high-order bits are incremented by six, producing the proper BCD digit in the high-order nibble. Again, this sets the carry flag if there is a carry-out of the high-order bits, but does not clear the carry. The carry flag thus indicates if the sum of the original two BCD variables is greater than 100, allowing multiple precision decimal addition. OV is not affected. All of this occurs during the one instruction cycle. Essentially, this instruction performs the decimal conversion by adding 00H, 06H, 60H, or 66H to the Accumulator, depending on initial Accumulator and PSW conditions. Note: DA A cannot simply convert a hexadecimal number in the Accumulator to BCD notation, nor does DAA apply to decimal subtraction.

DEC byteDecrement Byte variable  (details)
<byte> = <byte> – 1
affected flags: C, OV, AC
addresing modes: direct, indirect, register
MnemonicOperandsBytesPeriodsDescription
DECA112Decrement Accumulator  (hex codes)
Instruction1. Byte
DEC A14
DECRn112Decrement Register  (hex codes)
Instruction1. Byte
DEC R018
DEC R119
DEC R21A
DEC R31B
DEC R41C
DEC R51D
DEC R61E
DEC R71F
DECdirect212Decrement direct byte  (hex codes)
Instruction1. Byte2. Byte
DEC data addr15data addr
DEC@Ri112Decrement indirect RAM  (hex codes)
Instruction1. Byte
DEC @R016
DEC @R117

DEC byte decrements the variable indicated by 1. An original value of 00H underflows to 0FFH. No flags are affected. Four operand addressing modes are allowed: accumulator, register, direct, or register-indirect. Note: When this instruction is used to modify an output port, the value used as the original port data will be read from the output data latch, not the input pins.

DIV ABDivide Accumulator by B register  (details)
A = Int [A/B]; B = Mod [A/B]
affected flags: OV
note: ACC and B only
MnemonicOperandsBytesPeriodsDescription
DIVAB148Divide A by B  (hex codes)
Instruction1. Byte
DIV AB84

DIV AB divides the unsigned eight-bit integer in the Accumulator by the unsigned eight-bit integer in register B. The Accumulator receives the integer part of the quotient; register B receives the integer remainder. The carry and OV flags are cleared. Exception: if B had originally contained 00H, the values returned in the Accumulator and B-register are undefined and the overflow flag are set. The carry flag is cleared in any case.

DJNZ <byte>,<rel-addr>Decrement and Jump if Not Zero  (details)
Decrement and jump if not zero
affected flags: C, OV, AC
addresing modes: direct, register
MnemonicOperandsBytesPeriodsDescription
DJNZRn,rel224Decrement register and Jump if Not Zero  (hex codes)
Instruction1. Byte2. Byte
DJNZ R0,code addrD8code addr
DJNZ R1,code addrD9code addr
DJNZ R2,code addrDAcode addr
DJNZ R3,code addrDBcode addr
DJNZ R4,code addrDCcode addr
DJNZ R5,code addrDDcode addr
DJNZ R6,code addrDEcode addr
DJNZ R7,code addrDFcode addr
DJNZdirect,rel324Decrement direct byte and Jump if Not Zero  (hex codes)
Instruction1. Byte2. Byte3. Byte
DJNZ data addr,code addrD5data addrcode addr

DJNZ decrements the location indicated by 1, and branches to the address indicated by the second operand if the resulting value is not zero. An original value of 00H underflows to 0FFH. No flags are affected. The branch destination is computed by adding the signed relative-displacement value in the last instruction byte to the PC, after incrementing the PC to the first byte of the following instruction. The location decremented may be a register or directly addressed byte. Note: When this instruction is used to modify an output port, the value used as the original port data will be read from the output data latch, not the input pins.

INC <byte>Increment Byte variable  (details)
<byte> = <byte> + 1
affected flags: C, OV, AC
addresing modes: direct, indirect, register
MnemonicOperandsBytesPeriodsDescription
INCA112Increment Accumulator  (hex codes)
Instruction1. Byte
INC A04
INCRn112Increment register  (hex codes)
Instruction1. Byte
INC R008
INC R109
INC R20A
INC R30B
INC R40C
INC R50D
INC R60E
INC R70F
INCdirect212Increment direct byte  (hex codes)
Instruction1. Byte2. Byte
INC data addr05data addr
INC@Ri112Increment direct RAM  (hex codes)
Instruction1. Byte
INC @R006
INC @R107

INC increments the indicated variable by 1. An original value of 0FFH overflows to 00H. No flags are affected. Three addressing modes are allowed: register, direct, or register-indirect. Note: When this instruction is used to modify an output port, the value used as the original port data will be read from the output data latch, not the input pins.

INC DPTRIncrement Data Pointer  (details)
DPTR = DPTR + 1
affected flags: C, OV, AC
note: Data Pointer only
MnemonicOperandsBytesPeriodsDescription
INCDPTR124Increment Data Pointer  (hex codes)
Instruction1. Byte
INC DPTRA3

INC DPTR increments the 16-bit data pointer by 1. A 16-bit increment (modulo 216) is performed, and an overflow of the low-order byte of the data pointer (DPL) from 0FFH to 00H increments the high-order byte (DPH). No flags are affected. This is the only 16-bit register which can be incremented.

JB blt,relJump if Bit is set  (details)
Jump if bit = 1
affected flags: C, OV, AC
MnemonicOperandsBytesPeriodsDescription
JBbit,rel324Jump if direct Bit is set  (hex codes)
Instruction1. Byte2. Byte3. Byte
JB bit addr,code addr20bit addrcode addr

If the indicated bit is a one, JB jump to the address indicated; otherwise, it proceeds with the next instruction. The branch destination is computed by adding the signed relative-displacement in the third instruction byte to the PC, after incrementing the PC to the first byte of the next instruction. The bit tested is not modified. No flags are affected.

JBC bit,relJump if Bit is set and Clear Bit  (details)
Jump if bit = 1; bit = 0
affected flags: C, OV, AC
MnemonicOperandsBytesPeriodsDescription
JBCbit,rel324Jump if direct Bit is set & clear bit  (hex codes)
Instruction1. Byte2. Byte3. Byte
JBC bit addr,code addr10bit addrcode addr

If the indicated bit is one, JBC branches to the address indicated; otherwise, it proceeds with the next instruction. The bit will not be cleared if it is already a zero. The branch destination is computed by adding the signed relative-displacement in the third instruction byte to the PC, after incrementing the PC to the first byte of the next instruction. No flags are affected. Note: When this instruction is used to test an output pin, the value used as the original data will be read from the output data latch, not the input pin.

JC relJump if Carry flag is set  (details)
Jump if C = 1
affected flags: C, OV, AC
MnemonicOperandsBytesPeriodsDescription
JCrel224Jump if Carry is set  (hex codes)
Instruction1. Byte2. Byte
JC code addr40code addr

If the carry flag is set, JC branches to the address indicated; otherwise, it proceeds with the next instruction. The branch destination is computed by adding the signed relative-displacement in the second instruction byte to the PC, after incrementing the PC twice. No flags are affected.

JMP @A+DPTRJump indirect relative to the DPTR  (details)
Jump to A + DPTR
affected flags: C, OV, AC
MnemonicOperandsBytesPeriodsDescription
JMP@A+DPTR124Jump indirect relative to the DPTR  (hex codes)
Instruction1. Byte
JMP @A+DPTR73

JMP @A+DPTR adds the eight-bit unsigned contents of the Accumulator with the 16-bit data pointer and loads the resulting sum to the program counter. This is the address for subsequent instruction fetches. Sixteen-bit addition is performed (modulo 216): a carry-out from the low-order eight bits propagates through the higher-order bits. Neither the Accumulator nor the Data Pointer is altered. No flags are affected.

JNB bit,relJump if Bit is not set  (details)
Jump if bit = 0
affected flags: C, OV, AC
MnemonicOperandsBytesPeriodsDescription
JNBbit,rel324Jump if direct Bit is Not set  (hex codes)
Instruction1. Byte2. Byte3. Byte
JNB bit addr,code addr30bit addrcode addr

If the indicated bit is a 0, JNB branches to the indicated address; otherwise, it proceeds with the next instruction. The branch destination is computed by adding the signed relative-displacement in the third instruction byte to the PC, after incrementing the PC to the first byte of the next instruction. The bit tested is not modified. No flags are affected.

JNC relJump if Carry flag is not set  (details)
Jump if C = 0
affected flags: C, OV, AC
MnemonicOperandsBytesPeriodsDescription
JNCrel224Jump if Carry not set  (hex codes)
Instruction1. Byte2. Byte
JNC code addr50code addr

If the carry flag is a 0, JNC branches to the address indicated; otherwise, it proceeds with the next instruction. The branch destination is computed by adding the signal relative-displacement in the second instruction byte to the PC, after incrementing the PC twice to point to the next instruction. The carry flag is not modified.

JNZ relJump if Accumulator is not zero  (details)
Jump if A <> 0
affected flags: C, OV, AC
note: Accumulator only
MnemonicOperandsBytesPeriodsDescription
JNZrel224Jump if Accumulator is Not Zero  (hex codes)
Instruction1. Byte2. Byte
JNZ code addr70code addr

If any bit of the Accumulator is a one, JNZ branches to the indicated address; otherwise, it proceeds with the next instruction. The branch destination is computed by adding the signed relative-displacement in the second instruction byte to the PC, after incrementing the PC twice. The Accumulator is not modified. No flags are affected.

JZ relJump if Accumulator is zero  (details)
Jump if A = 0
affected flags: C, OV, AC
note: Accumulator only
MnemonicOperandsBytesPeriodsDescription
JZrel224Jump if Accumulator is Zero  (hex codes)
Instruction1. Byte2. Byte
JZ code addr60code addr

If all bits of the Accumulator are 0, JZ branches to the address indicated; otherwise, it proceeds with the next instruction. The branch destination is computed by adding the signed relative-displacement in the second instruction byte to the PC, after incrementing the PC twice. The Accumulator is not modified. No flags are affected.

LCALL addr16Long subroutine call  (details)
affected flags: C, OV, AC
MnemonicOperandsBytesPeriodsDescription
LCALLaddr16324Long Subroutine Call  (hex codes)
Instruction1. Byte2. Byte3. Byte
LCALL code addr12code addrode addr

LCALL calls a subroutine located at the indicated address. The instruction adds three to the program counter to generate the address of the next instruction and then pushes the 16-bit result onto the stack (low byte first), incrementing the Stack Pointer by two. The high-order and low-order bytes of the PC are then loaded, respectively, with the second and third bytes of the LCALL instruction. Program execution continues with the instruction at this address. The subroutine may therefore begin anywhere in the full 64K byte program memory address space. No flags are affected.

LJMP addr16Long jump  (details)
affected flags: C, OV, AC
MnemonicOperandsBytesPeriodsDescription
LJMPaddr16324Long Jump  (hex codes)
Instruction1. Byte2. Byte3. Byte
LJMP code addr02code addrode addr

LJMP causes an unconditional branch to the indicated address, by loading the high-order and low-order bytes of the PC (respectively) with the second and third instruction bytes. The destination may therefore be anywhere in the full 64K program memory address space. No flags are affected.

MOV <dest-byte>,<src-byte>Move Byte variable  (details)
<dest> = <src>
affected flags: C, OV, AC
addresing modes: direct, indirect, register, constant
MnemonicOperandsBytesPeriodsDescription
MOVA,Rn112Move register to Accumulator  (hex codes)
Instruction1. Byte
MOV A,R0E8
MOV A,R1E9
MOV A,R2EA
MOV A,R3EB
MOV A,R4EC
MOV A,R5ED
MOV A,R6EE
MOV A,R7EF
MOVA,direct212Move direct byte to Accumulator  (hex codes)
Instruction1. Byte2. Byte
MOV A,data addrE5data addr
MOVA,@Ri112Move indirect RAM to Accumulator  (hex codes)
Instruction1. Byte
MOV A,@R0E6
MOV A,@R1E7
MOVA,#data212Move immediate data to Accumulator  (hex codes)
Instruction1. Byte2. Byte
MOV A,#data74#data
MOVRn,A112Move Accumulator to register  (hex codes)
Instruction1. Byte
MOV R0,AF8
MOV R1,AF9
MOV R2,AFA
MOV R3,AFB
MOV R4,AFC
MOV R5,AFD
MOV R6,AFE
MOV R7,AFF
MOVRn,direct224Move direct byte to register  (hex codes)
Instruction1. Byte2. Byte
MOV R0,data addrA8data addr
MOV R1,data addrA9data addr
MOV R2,data addrAAdata addr
MOV R3,data addrABdata addr
MOV R4,data addrACdata addr
MOV R5,data addrADdata addr
MOV R6,data addrAEdata addr
MOV R7,data addrAFdata addr
MOVRn,#data212Move immediate data to register  (hex codes)
Instruction1. Byte2. Byte
MOV R0,#data78#data
MOV R1,#data79#data
MOV R2,#data7A#data
MOV R3,#data7B#data
MOV R4,#data7C#data
MOV R5,#data7D#data
MOV R6,#data7E#data
MOV R7,#data7F#data
MOVdirect,A212Move Accumulator to direct byte  (hex codes)
Instruction1. Byte2. Byte
MOV data addr,AF5data addr
MOVdirect,Rn224Move register to direct byte  (hex codes)
Instruction1. Byte2. Byte
MOV data addr,R088data addr
MOV data addr,R189data addr
MOV data addr,R28Adata addr
MOV data addr,R38Bdata addr
MOV data addr,R48Cdata addr
MOV data addr,R58Ddata addr
MOV data addr,R68Edata addr
MOV data addr,R78Fdata addr
MOVdirect,direct324Move direct byte to direct  (hex codes)
Instruction1. Byte2. Byte3. Byte
MOV data addr,data addr85data addrdata addr
MOVdirect,@Ri224Move indirect RAM to direct byte  (hex codes)
Instruction1. Byte2. Byte
MOV data addr,@R086data addr
MOV data addr,@R187data addr
MOVdirect,#data324Move immediate data to direct byte  (hex codes)
Instruction1. Byte2. Byte3. Byte
MOV data addr,#data75data addr#data
MOV@Ri,A112Move Accumulator to indirect RAM  (hex codes)
Instruction1. Byte
MOV @R0,AF6
MOV @R1,AF7
MOV@Ri,direct224Move direct byte to indirect RAM  (hex codes)
Instruction1. Byte2. Byte
MOV @R0,data addrA6data addr
MOV @R1,data addrA7data addr
MOV@Ri,#data212Move immediate data to indirect RAM  (hex codes)
Instruction1. Byte2. Byte
MOV @R0,#data76#data
MOV @R1,#data77#data

The byte variable indicated by the second operand is copied into the location specified by the first operand. The source byte is not affected. No other register or flag is affected. This is by far the most flexible operation. Fifteen combinations of source and destination addressing modes are allowed.

MOV <dest-bit>,<src-bit>Move Bit data  (details)
<dest-bit> = <src-bit>
affected flags: C, OV, AC
MnemonicOperandsBytesPeriodsDescription
MOVC,bit212Move direct bit to Carry  (hex codes)
Instruction1. Byte2. Byte
MOV C,bit addrA2bit addr
MOVbit,C224Move Carry to direct bit  (hex codes)
Instruction1. Byte2. Byte
MOV bit addr,C92bit addr

MOV &lt;dest-bit&gt;,&lt;src-bit&gt; copies the Boolean variable indicated by the second operand into the location specified by the first operand. One of the operands must be the carry flag; the other may be any directly addressable bit. No other register or flag is affected.

MOV DPTR,#data16Load Data Pointer with a 16-bit constant  (details)
DPTR = 16-bit immediate constant
affected flags: C, OV, AC
addresing modes: constant
MnemonicOperandsBytesPeriodsDescription
MOVDPTR,#data16324Load Data Pointer with a 16-bit constant  (hex codes)
Instruction1. Byte2. Byte3. Byte
MOV DPTR,#data90#datadata

MOV DPTR,#data16 loads the Data Pointer with the 16-bit constant indicated. The 16-bit constant is loaded into the second and third bytes of the instruction. The second byte (DPH) is the high-order byte, while the third byte (DPL) holds the lower-order byte. No flags are affected. This is the only instruction which moves 16 bits of data at once.

MOVC A,@A+ <base-reg>Move Code byte relative to Accumulator + Register  (details)
Read Pgm Memory at (A + DPTR), Read Pgm Memory at (A + PC)
affected flags: C, OV, AC
MnemonicOperandsBytesPeriodsDescription
MOVCA,@A+DPTR124Move Code byte relative to DPTR to Acc  (hex codes)
Instruction1. Byte
MOVC A,@A+DPTR93
MOVCA,@A+PC124Move Code byte relative to PC to Acc  (hex codes)
Instruction1. Byte
MOVC A,@A+PC83

The MOVC instructions load the Accumulator with a code byte or constant from program memory. The address of the byte fetched is the sum of the original unsigned 8-bit Accumulator contents and the contents of a 16-bit base register, which may be either the Data Pointer or the PC. In the latter case, the PC is incremented to the address of the following instruction before being added with the Accumulator; otherwise the base register is not altered. Sixteen-bit addition is performed so a carry-out from the low-order eight bits may propagate through higher-order bits. No flags are affected.

MOVX <dest-byte>,<src-byte>Move external byte variable  (details)
Read?Write external RAM @Ri
affected flags: C, OV, AC
note: Ri, DPTR
MnemonicOperandsBytesPeriodsDescription
MOVXA,@Ri124Move External RAM (8- bit addr) to Acc  (hex codes)
Instruction1. Byte
MOVX A,@R0E2
MOVX A,@R1E3
MOVXA,@DPTR124Move Exernal RAM (16- bit addr) to Acc  (hex codes)
Instruction1. Byte
MOVX A,@DPTRE0
MOVX@Ri,A124Move Acc to External RAM (8-bit addr)  (hex codes)
Instruction1. Byte
MOVX @R0,AF2
MOVX @R1,AF3
MOVX@DPTR,A124Move Acc to External RAM (16-bit addr)  (hex codes)
Instruction1. Byte
MOVX @DPTR,AF0

The MOVX instructions transfer data between the Accumulator and a byte of external data memory, which is why “X” is appended to MOV. There are two types of instructions, differing in whether they provide an 8-bit or 16-bit indirect address to the external data RAM. In the first type, the contents of R0 or R1 in the current register bank provide an 8-bit address multiplexed with data on P0. Eight bits are sufficient for external I/O expansion decoding or for a relatively small RAM array. For somewhat larger arrays, any output port pins can be used to output higher-order address bits. These pins are controlled by an output instruction preceding the MOVX. In the second type of MOVX instruction, the Data Pointer generates a 16-bit address. P2 outputs the high-order eight address bits (the contents of DPH), while P0 multiplexes the low-order eight bits (DPL) with data. The P2 Special Function Register retains its previous contents, while the P2 output buffers emit the contents of DPH. This form of MOVX is faster and more efficient when accessing very large data arrays (up to 64K bytes), since no additional instructions are needed to set up the output ports. It is possible to use both MOVX types in some situations. A large RAM array with its high-order address lines driven by P2 can be addressed via the Data Pointer, or with code to output high-order address bits to P2, followed by a MOVX instruction using R0 or R1.

MUL ABMultiply Accumulator and B register  (details)
B:A = B × A
affected flags: OV
note: ACC and B only
MnemonicOperandsBytesPeriodsDescription
MULAB148Multiply A & B  (hex codes)
Instruction1. Byte
MUL ABA4

MUL AB multiplies the unsigned 8-bit integers in the Accumulator and register B. The low-order byte of the 16-bit product is left in the Accumulator, and the high-order byte in B. If the product is greater than 255 (0FFH), the overflow flag is set; otherwise it is cleared. The carry flag is always cleared.

NOP No operation  (details)
No operation
affected flags: C, OV, AC
MnemonicOperandsBytesPeriodsDescription
NOP112No Operation  (hex codes)
Instruction1. Byte
NOP 00

Execution continues at the following instruction. Other than the PC, no registers or flags are affected.

ORL <dest-byte>,<src-byte>Logical OR for byte variables  (details)
affected flags: C, OV, AC
MnemonicOperandsBytesPeriodsDescription
ORLA,Rn112OR register to Accumulator  (hex codes)
Instruction1. Byte
ORL A,R048
ORL A,R149
ORL A,R24A
ORL A,R34B
ORL A,R44C
ORL A,R54D
ORL A,R64E
ORL A,R74F
ORLA,direct212OR direct byte to Accumulator  (hex codes)
Instruction1. Byte2. Byte
ORL A,data addr45data addr
ORLA,@Ri112OR indirect RAM to Accumulator  (hex codes)
Instruction1. Byte
ORL A,@R046
ORL A,@R147
ORLA,#data212OR immediate data to Accumulator  (hex codes)
Instruction1. Byte2. Byte
ORL A,#data44#data
ORLdirect,A212OR Accumulator to direct byte  (hex codes)
Instruction1. Byte2. Byte
ORL data addr,A42data addr
ORLdirect,#data324OR immediate data to direct byte  (hex codes)
Instruction1. Byte2. Byte3. Byte
ORL data addr,#data43data addr#data

ORL performs the bitwise logical-OR operation between the indicated variables, storing the results in the destination byte. No flags are affected. The two operands allow six addressing mode combinations. When the destination is the Accumulator, the source can use register, direct, register-indirect, or immediate addressing; when the destination is a direct address, the source can be the Accumulator or immediate data. Note: When this instruction is used to modify an output port, the value used as the original port data is read from the output data latch, not the input pins.

ORL C,<src-bit>Logical OR for Carry bit and Bit variable  (details)
C = C OR bit
affected flags: C, OV, AC
MnemonicOperandsBytesPeriodsDescription
ORLC,bit224OR direct bit to Carry  (hex codes)
Instruction1. Byte2. Byte
ORL C,bit addr72bit addr
ORLC,/bit224OR complement of direct bit to Carry  (hex codes)
Instruction1. Byte2. Byte
ORL C,/bit addrA0/bit addr

Set the carry flag if the Boolean value is a logical 1; leave the carry in its current state otherwise. A slash ( / ) preceding the operand in the assembly language indicates that the logical complement of the addressed bit is used as the source value, but the source bit itself is not affected. No other flags are affected.

POP directPop Byte from stack  (details)
MOV <dest>, “@SP”; DEC SP
affected flags: C, OV, AC
addresing modes: direct
MnemonicOperandsBytesPeriodsDescription
POPdirect224Pop direct byte from stack  (hex codes)
Instruction1. Byte2. Byte
POP data addrD0data addr

The contents of the internal RAM location addressed by the Stack Pointer is read, and the Stack Pointer is decremented by one. The value read is then transferred to the directly addressed byte indicated. No flags are affected.

PUSH directPush Byte into stack  (details)
INC SP; MOV “@SP”, <scr>
affected flags: C, OV, AC
addresing modes: direct
MnemonicOperandsBytesPeriodsDescription
PUSHdirect224Push direct byte into stack  (hex codes)
Instruction1. Byte2. Byte
PUSH data addrC0data addr

The Stack Pointer is incremented by one. The contents of the indicated variable is then copied into the internal RAM location addressed by the Stack Pointer. Otherwise no flags are affected.

RET Return from subroutine  (details)
Return from subroutine
affected flags: C, OV, AC
MnemonicOperandsBytesPeriodsDescription
RET124Return from Subroutine  (hex codes)
Instruction1. Byte
RET 22

RET pops the high- and low-order bytes of the PC successively from the stack, decrementing the Stack Pointer by two. Program execution continues at the resulting address, generally the instruction immediately following an ACALL or LCALL. No flags are affected.

RETI Return from interrupt  (details)
Return from interrupt
affected flags: C, OV, AC
MnemonicOperandsBytesPeriodsDescription
RETI124Return from interrupt  (hex codes)
Instruction1. Byte
RETI 32

RETI pops the high- and low-order bytes of the PC successively from the stack and restores the interrupt logic to accept additional interrupts at the same priority level as the one just processed. The Stack Pointer is left decremented by two. No other registers are affected; the PSW is not automatically restored to its pre-interrupt status. Program execution continues at the resulting address, which is generally the instruction immediately after the point at which the interrupt request was detected. If a lower- or same-level interrupt was pending when the RETI instruction is executed, that one instruction is executed before the pending interrupt is processed.

RL ARotate Accumulator Left  (details)
affected flags: C, OV, AC
MnemonicOperandsBytesPeriodsDescription
RLA112Rotate Accumulator Left  (hex codes)
Instruction1. Byte
RL A23

The eight bits in the Accumulator are rotated one bit to the left. Bit 7 is rotated into the bit 0 position. No flags are affected.

RLC ARotate Accumulator Left through the Carry flag  (details)
affected flags: C
MnemonicOperandsBytesPeriodsDescription
RLCA112Rotate Accumulator Left through the Carry  (hex codes)
Instruction1. Byte
RLC A33

The eight bits in the Accumulator and the carry flag are together rotated one bit to the left. Bit 7 moves into the carry flag; the original state of the carry flag moves into the bit 0 position. No other flags are affected.

RR ARotate Accumulator Right  (details)
affected flags: C, OV, AC
MnemonicOperandsBytesPeriodsDescription
RRA112Rotate Accumulator Right  (hex codes)
Instruction1. Byte
RR A03

The eight bits in the Accumulator are rotated one bit to the right. Bit 0 is rotated into the bit 7 position. No flags are affected.

RRC ARotate Accumulator Right through Carry flag  (details)
affected flags: C
MnemonicOperandsBytesPeriodsDescription
RRCA112Rotate Accumulator Right through the Carry  (hex codes)
Instruction1. Byte
RRC A13

The eight bits in the Accumulator and the carry flag are together rotated one bit to the right. Bit 0 moves into the carry flag; the original value of the carry flag moves into the bit 7 position. No other flags are affected.

SETB <bit>Set Bit data  (details)
bit = 1
affected flags: C, OV, AC
MnemonicOperandsBytesPeriodsDescription
SETBC112Set Carry  (hex codes)
Instruction1. Byte
SETB CD3
SETBbit212Set direct bit  (hex codes)
Instruction1. Byte2. Byte
SETB bit addrD2bit addr

SETB sets the indicated bit to one. SETB can operate on the carry flag or any directly addressable bit. No other flags are affected.

SJMP relShort jump  (details)
Jump to addr
affected flags: C, OV, AC
MnemonicOperandsBytesPeriodsDescription
SJMPrel224Short Jump (relative addr)  (hex codes)
Instruction1. Byte2. Byte
SJMP code addr80code addr

Program control branches unconditionally to the address indicated. The branch destination is computed by adding the signed displacement in the second instruction byte to the PC, after incrementing the PC twice. Therefore, the range of destinations allowed is from 128 bytes preceding this instruction 127 bytes following it.

SUBB A,<src-byte>Subtract Byte with Carry from Accumullator  (details)
A = A – <byte> – C
affected flags: C, OV, AC
addresing modes: direct, indirect, register, constant
MnemonicOperandsBytesPeriodsDescription
SUBBA,Rn112Subtract Register from Acc with borrow  (hex codes)
Instruction1. Byte
SUBB A,R098
SUBB A,R199
SUBB A,R29A
SUBB A,R39B
SUBB A,R49C
SUBB A,R59D
SUBB A,R69E
SUBB A,R79F
SUBBA,direct212Subtract direct byte from Acc with borrow  (hex codes)
Instruction1. Byte2. Byte
SUBB A,data addr95data addr
SUBBA,@Ri112Subtract indirect RAM from ACC with borrow  (hex codes)
Instruction1. Byte
SUBB A,@R096
SUBB A,@R197
SUBBA,#data212Subtract immediate data from Acc with borrow  (hex codes)
Instruction1. Byte2. Byte
SUBB A,#data94#data

SUBB subtracts the indicated variable and the carry flag together from the Accumulator, leaving the result in the Accumulator. SUBB sets the carry (borrow) flag if a borrow is needed for bit 7 and clears C otherwise. (If C was set before executing a SUBB instruction, this indicates that a borrow was needed for the previous step in a multiple-precision subtraction, so the carry is subtracted from the Accumulator along with the source operand.) AC is set if a borrow is needed for bit 3 and cleared otherwise. OV is set if a borrow is needed into bit 6, but not into bit 7, or into bit 7, but not bit 6. When subtracting signed integers, OV indicates a negative number produced when a negative value is subtracted from a positive value, or a positive result when a positive number is subtracted from a negative number. The source operand allows four addressing modes: register, direct, register-indirect, or immediate.

SWAP ASwap nibbles within the Accumulator  (details)
affected flags: C, OV, AC
MnemonicOperandsBytesPeriodsDescription
SWAPA112Swap nibbles within the Accumulator  (hex codes)
Instruction1. Byte
SWAP AC4

SWAP A interchanges the low- and high-order nibbles (four-bit fields) of the Accumulator (bits 3 through 0 and bits 7 through 4). The operation can also be thought of as a 4-bit rotate instruction. No flags are affected.

XCH A,<byte>Exchange Accumulator with byte variable  (details)
ACC and <byte> Exchange Data
affected flags: C, OV, AC
addresing modes: direct, indirect, register
MnemonicOperandsBytesPeriodsDescription
XCHA,Rn112Exchange register with Accumulator  (hex codes)
Instruction1. Byte
XCH A,R0C8
XCH A,R1C9
XCH A,R2CA
XCH A,R3CB
XCH A,R4CC
XCH A,R5CD
XCH A,R6CE
XCH A,R7CF
XCHA,direct212Exchange direct byte with Accumulator  (hex codes)
Instruction1. Byte2. Byte
XCH A,data addrC5data addr
XCHA,@Ri112Exchange indirect RAM with Accumulator  (hex codes)
Instruction1. Byte
XCH A,@R0C6
XCH A,@R1C7

XCH loads the Accumulator with the contents of the indicated variable, at the same time writing the original Accumulator contents to the indicated variable. The source/destination operand can use register, direct, or register-indirect addressing.

XCHD A,@RiExchange Byte with Accumulator  (details)
ACC and @ Ri exchange low nibbles
affected flags: C, OV, AC
addresing modes: indirect
MnemonicOperandsBytesPeriodsDescription
XCHDA,@Ri112Exchange low-order Digit indirect RAM with Acc  (hex codes)
Instruction1. Byte
XCHD A,@R0D6
XCHD A,@R1D7

XCHD exchanges the low-order nibble of the Accumulator (bits 3 through 0), generally representing a hexadecimal or BCD digit, with that of the internal RAM location indirectly addressed by the specified register. The high-order nibbles (bits 7-4) of each register are not affected. No flags are affected.

XRL <dest-byte>,<src-byte>Logical Exclusive OR for Byte variables  (details)
affected flags: C, OV, AC
MnemonicOperandsBytesPeriodsDescription
XRLA,Rn112Exclusive-OR register to Accumulator  (hex codes)
Instruction1. Byte
XRL A,R068
XRL A,R169
XRL A,R26A
XRL A,R36B
XRL A,R46C
XRL A,R56D
XRL A,R66E
XRL A,R76F
XRLA,direct212Exclusive-OR direct byte to Accumulator  (hex codes)
Instruction1. Byte2. Byte
XRL A,data addr65data addr
XRLA,@Ri112Exclusive-OR indirect RAM to Accumulator  (hex codes)
Instruction1. Byte
XRL A,@R066
XRL A,@R167
XRLA,#data212Exclusive-OR immediate data to Accumulator  (hex codes)
Instruction1. Byte2. Byte
XRL A,#data64#data
XRLdirect,A212Exclusive-OR Accumulator to direct byte  (hex codes)
Instruction1. Byte2. Byte
XRL data addr,A62data addr
XRLdirect,#data324Exclusive-OR immediate data to direct byte  (hex codes)
Instruction1. Byte2. Byte3. Byte
XRL data addr,#data63data addr#data

XRL performs the bitwise logical Exclusive-OR operation between the indicated variables, storing the results in the destination. No flags are affected. The two operands allow six addressing mode combinations. When the destination is the Accumulator, the source can use register, direct, register-indirect, or immediate addressing; when the destination is a direct address, the source can be the Accumulator or immediate data. Note: When this instruction is used to modify an output port, the value used as the original port data is read from the output data latch, not the input pins.